Block write circuit and method for wide data path memory device

ABSTRACT

A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to receive respective data signals, and a plurality of array groups each including a plurality of arrays and each array includes a plurality of memory cells. A plurality of input/output line groups each include a plurality of input/output lines coupled to the arrays of an associated array group. The block write circuit comprises a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective data lines in an associated data line group. Each write driver circuit includes an input and develops a data signal on its output responsive to a data signal applied on its input. A multiplexer circuit includes a plurality of inputs coupled to respective data terminals, and a plurality of output subgroups. Each output subgroup is associated with a respective input, and each output group includes a plurality of outputs coupled to the write driver circuits in an associated write driver group. The multiplexer circuit operates responsive to a control in a block write mode to couple each of its inputs to the outputs in the associated output subgroup. A masking circuit may also mask data from respective input/output lines responsive to masking signals.

TECHNICAL FIELD

The present invention relates generally to semiconductor memories, andmore specifically to a method and circuit for performing a block writedata transfer in a memory device having a wide internal data path.

BACKGROUND OF THE INVENTION

A computer system typically includes a video system that displaysinformation for a computer user. In a typical video system, a videocontroller accesses data stored in video memory and drives a displayunit, such as a cathode ray tube, to display the stored information, asunderstood by one skilled in the art. The video memory typicallyincludes specialized dynamic random access memories (“DRAM”), such as asynchronous graphics DRAM (“SGRAM”), which include special functionsthat enable the video controller to more efficiently access stored videodata and drive the display unit. Such special functions typicallyinclude bit-masking, byte-masking, and block write functions. Inbit-masking, selected bits of write data applied on a data bus of theSGRAM are masked from corresponding addressed memory cells so the datastored in those cells is not overwritten. Byte-masking is analogous tobit-masking except that bytes of write data applied on the data bus areselectively masked from eight corresponding memory cells. The blockwrite function enables the SGRAM to transfer a single bit of data to agroup or block of memory cells, which reduces the time it takes totransfer the same data to a large number of memory cells. A typicalapplication of the block write function is writing data corresponding toa desired background color for a video screen to a plurality of memorycells in the SCRAM.

FIG. 1 is a functional block diagram of a portion of a conventionalSGRAM 100 including a conventional block write circuit 102 coupled to amemory-cell arrayed 104 including a plurality of memory cells (notshown) arranged in rows and columns. A block 106 of memory cells in thearray 104 is shown, and corresponds to a group of eight memory cells inan activated row in the array. A number of digit lines DL0-DL7 are showncoupled to respective memory cells in the block 106. One skilled in theart will realize the depiction of the array 104 has been simplified forease of explanation, and that components such as sense amplifiers andcomplementary signal lines have been omitted for the sake of brevity.

The block write circuit 102 includes a column mask decoder 108 receivinga number of column mask bits CM0-CM7 stored in a column mask register110. The column mask bits CM0-CM7 correspond to data placed onrespective data terminals DQ0-DQ7 coincident with a block write commandapplied to the SGRAM 100, as understood by one skilled in the art. Inresponse to the column mask bits CM0-CM7, the column mask decoder 108activates a number of column select signals CSEL0-CSEL7. When one of thecolumn mask bits CM0-CM7 is set, the column mask decoder 108 deactivatesthe corresponding column select signal CSEL0-CSEL7, and when one of themask bits CM0-CM7 is cleared, the column mask circuit 108 activates thecorresponding column select signal CSEL0-CSEL7. A number of input/outputtransistors 112a-h are coupled between the digit lines DL0-DL7,respectively, and an input/output or input/output line I/O1. Each of thetransistors 112a-h receives on its gate a respective one of the columnselect signals CSEL0-CSEL7. The transistors 112a-h each turn ON when theapplied one of the column select signals CSEL0-CSEL7 is active, andthereby couples the input/output line I/O1 to the corresponding digitlines DL0-DL7. When any of the column select signals CSEL0-CSEL7 isinactive, the corresponding transistors 112a-h turn OFF, isolating thecorresponding digit lines DL0-DL7 from the input/output line I/O1.

A write driver 114 receives on its input either a color bit CR0 or awrite data bit applied on the data terminal DQ0, and applies the data onits input to the input/output line I/O1 in response to a masking signal{overscore (M)} received on an enable input. An AND gate 116 developsthe mask signal {overscore (M)} in response to a byte-mask signal DQM0applied on a first input and a mask bit MR0 applied on a second input.When the mask bit MR0 is set low or the byte-mask signal is active high,the AND gate 116 drives the mask signal {overscore (M)} active low, andwhen the mask bit MR0 is cleared high and the byte-mask signal DQM0 isinactive low, the AND gate 116 drives the mask signal {overscore (M)}inactive high. In operation during a standard write operation,conventional address decode circuitry (not shown in FIG. 1) decodesaddress signals applied to the SGRAM 100 and activates a correspondingmemory cell in the array 104, as understood by one skilled in the art.The write driver 114 then transfers data applied on the terminal DQ0onto the input/output line I/O1 when the mask signal {overscore (M)} isinactive high, and places its output in a high-impedance state toisolate or “mask” this data from the input/output line I/O1 when themask signal {overscore (M)} is active low.

In operation during a block write data transfer, the block write circuit102 transfers the color bit CR0 to selected ones of the memory cells inthe block 106, as will now be described in more detail. During a blockwrite, the address decode circuitry once again decodes address signalsapplied to the SGRAM 100, and activates corresponding memory cells inthe array 104, as understood by one skilled in the art. If either themask bit MR0 is set or the byte-mask signal DQM0 is active high, thewrite driver 114 places its output in a high impedance state, maskingthe color bit CR0 from the memory cells in the block 106 independent ofthe state of the column select signals CSEL0-CSEL7. In this situation,the data stored in the block 106 is not altered during the block writeoperation. When the mask bit MR0 is cleared and the byte-mask signalDQM0 is inactive low, the write driver 114 places the color bit CR0 onthe input/output line I/O1, and the column mask decoder 108 activatesselected ones of the column select signals CSEL0-CSEL7 in response tothe column mask bits CM0-CM7. In response to the column select signalsCSEL0-CSEL7, selected ones of the transistors 112a-h turn ON, couplingthe corresponding digit lines DL0-DL7 to the input/output line I/O1. Thecolor bit CR0 is then transferred through the activated ones of thetransistors 112a-h and over the corresponding digit lines DL0-DL7 torespective memory cells in the block 106. If any of the column mask bitsCM0-CM7 is set, the corresponding one of the column select signalsCSEL0-CSEL7 is deactivated, turning off the associated one of thetransistors 112a-h and thereby masking the color bit CR0 from thecorresponding memory cell in the block 106. For example, when the columnmask bit CR6 is set, the column select signal CSEL6 is deactivated,turning OFF the transistor 112g and thereby masking the color bit CR0from the memory cell in the block 106 coupled to the digit line DL6. Inthis way, the column mask decoder 108 masks the color bit CR0 fromrespective cells within the block 18, which is known as “columnmasking.”

From this description, it is seen that during a block write, several ofthe transistors 112a-h are typically simultaneously activated, couplingseveral of the digit lines DL0-DL7 to the input/output line I/O1. Infact, when none of the column mask bits CM0-CM7 is set, all of thetransistors 112a-h are turned ON, coupling all of the digit linesDL0-DL7 to the input/output line I/O1. As more digit lines DL0-DL7 arecoupled to the input/output line I/O1, the load presented by theinput/output line I/O1 increases, and this increased load must be drivenby the write driver 114. The load presented by the input/output lineI/O1 increases because each of the digit lines DL0-DL7 coupled to theinput/output line I/O1 presents an additional parallel load the writedriver 114 must drive. The additional load presented by each of thedigit lines DL0-DL7 includes the load presented by a sense amplifier(not shown in FIG. 1) coupled to the digit line, along with theadditional capacitance presented by the digit line, as understood by oneskilled in the art. As a result of the additional load presented by theinput/output line I/O1, it takes longer for the write driver 114 todrive the voltage on the input/output line I/O1 to the desired level,and thereby increases the time it takes the conventional block writecircuit 102 to perform each block write data transfer. One skilled inthe art will appreciate that during standard write data transfers, asingle digit line DL is coupled to the input/output line I/O1, reducingthe load driven by the write driver 114 relative to block writetransfers, and thereby reducing the time required to perform suchstandard write transfers.

Although the conventional block write circuit 102 typically increasesthe time required for performing block write operations, the circuitperforms satisfactorily in most conventional SGRAMs. As the speed ofmicroprocessors and bandwidths of memory devices steadily increase,however, the time for performing block write operations becomes morecritical. In addition, the column masking performed by the conventionalblock write circuit 102 may be difficult to implement in many new memorydevices, such as packetized DRAMs and Embedded DRAMs, having very wideinternal data paths. The internal data path includes the input/outputlines I/O, and a wide internal data path accordingly includes more suchlines. With a wide internal data path, the number of input/output linesI/O associated with each array increases and the number of column selectsignals CSEL associated with each array typically decreases. The numberof column select lines decreases because for each column select signalCSEL more data is transferred out of the array on the input/output linesI/O. For example, in an array where each row includes 128 columns and 64input/output lines (i.e., a 64-bit internal data bus) are associatedwith the array, only two column select lines CSEL are required, one totransfer the data stored in the memory cells in the first 64 columnsonto the respective input/output lines, and a second column selectsignal to do the same for the data stored in the second 64 columns. Asthe number of column select signals CSEL decreases, the approachillustrated in FIG. 2 for performing column masking during block writeoperations may be difficult to implement since the column mask decoder108 no longer applies separate column select signals CSEL to each columnselect transistor. For example, in the array described above having 128columns of memory cells and 64 associated input/output lines, the columnselect transistors associated with the first 64 columns have their gatescoupled together to receive the first column select signal. In thissituation, individual column select transistors cannot be separatelyactivated since their respective gates are coupled together.

There is a need for a block write circuit in a memory device having awide internal data path that decreases the time required for performingblock write operations and performs column masking of bits within eachblock.

SUMMARY OF THE INVENTION

A block write circuit in a memory device performs block write operationsin a memory device having a wide internal data path. The memory deviceincludes at least one array having a plurality of memory cells arrangedin rows and columns. The array includes a plurality of digit lines, eachdigit line coupled to a plurality of memory cells in an associatedcolumn. According to one aspect of the present invention, the blockwrite circuit includes a plurality of input/output lines and a switchcircuit coupled between the input/output lines and the digit lines. Theswitch circuit selectively couples at least one digit line to eachinput/output line responsive to an address signal during a block writemode of operation. A plurality of driver circuits each includes aninput, and an output coupled to a respective input/output line, anddevelops a data signal on its output in response to a data signalapplied on its input. A multiplexer circuit has an input adapted toreceive a data signal and a plurality of outputs coupled to respectiveinputs of the driver circuits. The multiplexer circuit couples its inputto its outputs responsive to a control signal during the block writemode of operation.

According to another aspect of the present invention, the multiplexercircuit isolates its input from selected ones of outputs responsive tocolumn masking signals. In this way, the multiplexer masks data appliedon its input from corresponding input/output lines, and thereby masksthe data from corresponding memory cells in the array.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of one of a portion of an SGRAMincluding a conventional block write circuit.

FIG. 2 consisting of FIGS. 2A and 2B is a functional block diagram of aportion of a memory device having a wide data path coupled to a blockwrite circuit according to one embodiment of the present invention.

FIG. 3 is a functional block diagram of an Embedded DRAM having a memorydevice including the block write circuit of FIG. 2.

FIG. 4 is a functional block diagram of a computer system including theembedded DRAM of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 is a functional block diagram of a portion of a memory device 300having a wide internal data path 302 coupled to a block write circuit304 according to one embodiment of the present invention. The blockwrite circuit 304 operates in standard and block write modes to transferdata applied on a data bus DQ1-DQ32 over the wide internal data path 302to addressed memory cells in a plurality of arrays 306-320, as will beexplained in more detail below.

In the memory device 300, the wide internal data path 302 includes 128input/output lines I/O1 I/O128 that transfer data to and from addressedmemory cells in the arrays 306-320. Each of the arrays 306-320 includesa plurality of memory cells (not shown) arranged in rows and columns.The arrays 306-320 are arranged as shown, with adjacent arrays coupledto the same 32 input/output lines I/O1-I/O128 of the wide terminal datapath 302. For example, the arrays 306 and 308 are coupled to the datalines I/O1-I/032, arrays 310 and 312 are coupled to data linesI/O33-I/O64, and so on. The coupling of the arrays 318,320 to theinput/output lines I/O97-I/O128 is illustrated in more detail, and,although now shown for arrays 306-316, one skilled in the art willrealize these arrays are coupled to the associated data linesI/O1-I/O128 in the same manner. Each of the arrays 318,320 includes anumber of digit lines DL1-DLN coupled to memory cells in respectivecolumns in the array. The digit lines DL1-DLN are coupled tocorresponding input/output lines I/O97-I/O128 through respective columnselect transistors 321. A plurality of column select signals CSEL1-CSELXare applied to the respective gates of the column select transistors321. In the embodiment of FIG. 2, each of the column select signals CSELis typically applied to 32 column select transistors 321. One skilled inthe art will realize FIG. 2 is a simplified depiction of theinterconnection between the arrays 318,320 and correspondinginput/output lines I/O97-I/O128, and that additional components such assense amplifiers and complementary signal lines have been omitted forthe sake of brevity. In addition, the physical formation of the arrays306-320 and wide data path 302 is very different than in a conventionalmemory device, but is peripheral to the present invention and in theinterests of brevity will not be described in further detail. In thememory device 300, the numbers of arrays 306-320 and input/output linesI/O97-I/O128 will vary depending on the specific architecture of thememory device 300.

The operation of the arrays 306-320 is identical, and for the sake ofbrevity only the operation of the array 318 will be described in moredetail. As understood by one skilled in the art, the memory device 300also includes row and column address decode circuitry (not shown in FIG.2) that decode respective address signals applied to the memory deviceand access corresponding memory cells in the arrays 306-320. To transferdata between addressed memory cells in the array 318 and theinput/output lines I/O97-I/O128, the row address decode circuitrydecodes a row address applied to the memory device 300 and activates acorresponding row in the array 318. At this point, the data stored inthe memory cells in the activated row is placed on the respective digitlines DL1-DLN. The column address decode circuitry then decodes a columnaddress applied to the memory device 300, and activates thecorresponding one of the column select signals CSEL1-CSELX. The 32column select transistors 321 receiving the activated column selectsignal couple the associated digit lines DL1-DLN to the respectiveinput/output lines I/O97-I/O128. For example, when the signal CSEL1 isactivated, the digit lines DL1-DL32 are coupled through the activatedcolumn select transistors 321 to respective input/output linesI/O97-I/O128. At this point, data is transferred between theinput/output lines I/O97-I/O128 and the addressed memory cells. During aread operation, data stored in the addressed memory cells is transferredover the corresponding digit lines, through the column selecttransistors 321, and onto the input/output lines I/O97-I/O128. During awrite operation, write data on the input/output lines I/O97-I/O128 istransferred through the respective transistors 321 and over thecorresponding digit lines to the addressed memory cells.

The block write circuit 304 includes a plurality of input buffersBUF1-BUF32 receiving respective data signals applied on data terminalsDQ1-DQ32 of the memory device 300. A color register 312 is shown coupledbetween the data terminals DQ1-DQ32 and the input buffers BUF1-BUF32,and stores color bits CR1-CR32. The color register 322 applies the colorbits CR1-CR32 to the input buffers BUF1-BUF32, respectively, when theblock write circuit 304 operates in the block write mode, and otherwiseapplies data on the terminals DQ1-DQ32 to the buffers BUF1-BUF32,respectively, as will be explained in more detail below. The buffersBUF1-BUF32 further receive respective mask signals {overscore(M1)}-{overscore (M32)} from a mask circuit 324. Each of the buffersBUF1-BUF32 drives a signal on its output to the same logic level as asignal applied on its input when the associated mask signal is inactive,and places its output in a high impedance state when the associated masksignal is active. In this way, when any of the mask signals {overscore(M1)}-{overscore (M32)} is active, the corresponding ones of the buffersBUF1-BUF32 mask the data signals applied on their respective inputs.

The mask circuit 324 includes a plurality of AND gates AND1-AND32 thatdevelop the mask signals {overscore (M1)}-{overscore (M32)} onrespective outputs. The gates AND1-AND32 receive mask bits MR1-MR32 onrespective first inputs. The mask bits MR1-MR32 are stored in a maskregister 326 coupled to the data terminals DQ1-DQ32. Each of the gatesAND1-AND32 further receives one of four byte mask signals DQM0-DQM3 on asecond input, with only the byte mask signals DQM0 and DQM3 being, shownin FIG. 3. Each of the byte mask signal DQM0-DQM3 is applied to thesecond inputs of a group of eight of the gates AND1-AND32. Thus, thebyte mask signals DQM0, DQM1, DQM2, and DQM3 are applied to the secondinputs of the gates AND1-AND8, AND9-AND16, AND17-AND24, and AND25-AND32,respectively. Each of the gates AND1-AND32 drives the corresponding masksignal {overscore (M1)}-{overscore (M32)} active when either theassociated byte mask signal DQM0-DQM3 is active high or the associatedmask bit MR1-MR32 is set active low. For example, when the mask bit MR1is set or the byte mask signal DQM0 is active high, the gate AND1 drivesthe mask signal {overscore (M1)} active low. When the mask bit MR1 iscleared high, or the byte mask signal DQM0 is inactive low, the gateAND1 drives the mask signal {overscore (M1)} inactive high.

The block write circuit 304 further includes a plurality of multiplexersMUX1-MUX32 receiving the data signals output by the buffers BUF1-BUF32on respective inputs. Each of the multiplexers MUX1-MUX32 includes fouroutputs, and receives a plurality of address signals ADDR and a blockwrite signal BLKWRT. The signals ADDR and BLKWRT are shown applied onlyto the multiplexer MUX32, but these signals are actually applied to themultiplexers MUX1-MUX31 as well, and have been omitted merely tosimplify FIG. 2. The outputs of the multiplexers MUX1-MUX32 are coupledthrough respective write drivers WD1-WD128 to corresponding ones of theinput/output lines I/O1-I/O128. For example, the four outputs of themultiplexer MUX1 are coupled through the write drivers WD1, WD2, WD3,and WD4 to the input/output lines I/O1, 1/O2, 1/O3, and I/O4,respectively. Each of the write drivers WD1-WD128 drives a signal on itsoutput to the level of a signal applied on its input. The write driversWD1-WD128, buffers BUF1-BUF32, mask register 326 and color register 322are all conventional circuits, and well understood by those skilled inthe art.

In operation, each of the multiplexers MUX1-MUX32 operates in one of twomodes, a standard write mode and a block write mode. When the blockwrite signal BLKWRT is inactive, the multiplexers MUX1-MUX32 operate inthe standard write mode. In the standard write mode, each of themultiplexers MUX1-MUX32 couples its input to one of its outputs inresponse to the signals ADDR. In the block write mode, the block writesignal BLKWRT is active and each of the multiplexers MUX1-MUX32 couplesits input to all four of its outputs independent of the signals ADDR.

The overall operation of the block write circuit 304 will now bedescribed in more detail. For the following description, it will beassumed the desired mask bits MR1-MR32 have been stored in the maskregister 326, and the desired bits CR1-CR32 have similarly been storedin the color register 322. During operation, the address decodecircuitry decodes address signals applied to the memory device 300 andaccesses corresponding memory cells in the arrays 306-320. The blockwrite circuit 304 operates in a standard write mode and a block writemode corresponding to the two modes by the same names previouslydescribed for the multiplexers MUX1-MUX32. It will be assumed thatduring operation in both the standard and block write modes the addressdecode circuitry accesses memory cells such that single memory cells arecoupled to the respective input/output lines I/O1-I/O128, as will beexplained in more detail below. For example, in each of the arrays318,320, only one of the column select signals CSEL1-CSELX is activatedat a time such that only a single digit line DL is coupled to each ofthe input/output lines I/O97-I/O128. Furthermore, column select signalsCSEL1-CSELX in both arrays 318,320 are not simultaneously activated sothat digit lines DL in both arrays 318,320 are not simultaneouslycoupled to respective input/output lines I/O97-I/O128.

The block write circuit 304 operates in the standard write mode when theblock write signal BLKWRT is inactive. In the standard write mode, theblock write circuit 304 operates in one of three submodes, an unmaskedsubmode, a byte-masked submode, and a bit-masked submode. In theunmasked submode, all of the mask bits MR1-MR32 are cleared and all thebyte mask signals DQM0-DQM3 are inactive low, causing the mask circuit324 to drive the mask signals {overscore (M1)}-{overscore (M32)}inactive high and thereby enabling the buffers BUF1-BUF32 When thebuffers BUF1-BUF32 are enabled, data placed on the terminals DQ1-DQ32 istransferred through the buffers BUF1-BUF32, respectively, and applied tothe respective inputs of the multiplexers MUX1-MUX32. Each of themultiplexers MUX1-MUX32 transfers data applied on its input to one ofthe associated write drivers WD1-WD128 which, in turn, places the dataon the associated one of the input/output lines I/O1-I/O128 where thedata is thereafter transferred through activated column selecttransistors 321 and across corresponding digit lines DL to the addressedmemory cells in the arrays 306-320.

For example, assume that during the unmasked submode the address signalsADDR have values causing each of the multiplexers MUX1-MUX32 to transferthe data applied on its input to the bottom one of the associated writedriver circuits WD1-WD128. Thus, the multiplexer MUX1 transfers dataapplied on its input to the input of the write driver WD4. In thisexample, data applied on the terminals DQ1-DQ32 is transferred throughthe buffers BUF1-BUF32 to the multiplexers MUX1-MUX32 which, in turn,transfers the data to every fourth I/O line, 1/O4, I/O8, I/O12, . . .I/O 128 where it is then transferred through activated column selecttransistors 321 and across corresponding digit lines DL to addressedmemory cells in one of the arrays 318 and 320. In this way, during theunmasked submode, 32 bits of data applied on the terminals DQ1-DQ32 aretransferred to 32 corresponding addressed memory cells in one of thearrays 306-320.

In the byte-masked submode, the block write circuit 304 operatesidentically to the unmasked submode except that one of the byte masksignals DQM0-DQM3 is active high masking eight bits of data applied oneight corresponding terminals DQ1-DQ32. For example, when the byte masksignal DQM0 is active, the mask circuit 324 activates the mask signals{overscore (M1)}-{overscore (M8)} and thereby disables the buffersBUF1-BUF8, respectively. When the buffers BUF1-BUF8 are disabled, dataapplied on the terminals DQ1-DQ8 is masked and thus not transferred tocorresponding addressed memory cells in the arrays 306-320. Thus, eachof the byte mask signals DQM0-DQM3 masks a byte of data applied on theterminals DQ1-DQ32.

In the bit-masked submode, the block write circuit 304 once againoperates identically to the unmasked submode except that selected bitsof data applied on the data terminals DQ1-DQ32 are masked. The mask bitsMR1-MR32 stored in the mask register 326 determine which of the databits applied on the terminals DQ1-DQ32 are masked. For example, assumeonly the mask bit MR2 is set and all other mask bits are cleared. Inthis situation, data placed on the terminal DQ2 is masked and thus notstored in the corresponding addressed memory cell coupled to theinput/output lien I/O98. In this way, during the bit-masked submode themask bits MR1-MR32 are used to mask individual bits of data applied onthe terminals DQ1-DQ32.

The block write circuit 304 operates in the block write mode when theblock write signal BLKWRT is active. As previously described, when theblock write signal BLKWRT is active, each of the multiplexers MUX1-MUX32couples its input to all four of its outputs. During the block writemode, the address decode circuitry in the memory device 300 activates aplurality of column signals CSEL such that a single digit line DL iscoupled to each of the input/output lines I/O1-I/O128. For example, theaddress decode circuitry may activate the column select signals CSEL1 ofthe arrays 306, 310, 314, and 318, thereby coupling 32 digit lines DL ineach of these arrays to the 32 corresponding input/output linesI/O1-I/O128. During the block write mode, the block write circuit 304again operates in an unmasked submode, a byte-masked submode, and abit-masked submode, and the color bits CR1-CR32 stored in the colorregister 322 are applied to the inputs of the buffers BUF1-BUF32,respectively. In the unmasked submode, each of the color bits CR1-CR32is transferred through the associated one of the buffers BUF1-BUF32 andmultiplexers MUX1-MUX32 to four addressed memory cells in the arrays306-320. For example, the color bit CR1 is transferred through thebuffer BUF1 and through the multiplexer MUX1 to the respective inputs ofthe write drivers WD1-WD4, which, in turn, place this data on theinput/output lines I/O1, I/O2, I/O3, and I/O4, respectively. The colorbit CR1 data on the lines I/O1, I/O2, I/O3, and I/O4 is thereaftertransferred through activated column select transistors 321 and overcorresponding digit lines DL to the addressed memory cells in the arrays306-320. Thus, in the unmasked submode, the 32 color bits CR1-CR32 aretransferred to 128 addressed memory cells in activated ones of thearrays 306-320. In this way, the block write circuit 304 enables each ofthe color bits CR1-CR32 to be written to a plurality of memory cells inthe arrays 306-320.

During the byte-masked submode, the mask circuit 324 operates aspreviously described during the standard write mode of operation to maska byte of data applied to eight corresponding buffers BUF1-BUF32. Forexample, when the byte mask signal DQM0 is active high, the buffersBUF1-BUF8 are disabled masking the color bits CR1-CR8, respectively. Inthis situation, each of the multiplexers MUX1-MUX8 has its input datamasked which, in turn, masks the four bits of data output by each ofthese multiplexers during the block write mode. Thus, when the byte masksignal DQM0 is active, 32 bits of data that would normally be output bythe multiplexers MUX1-MUX8 are masked.

Finally, in the bit-masked submode, the mask bits MR1-MR32 mask selectedones of the color bits CR1-CR32. For example, assume the mask bit MR2 isset and all other mask bits are cleared. In this situation, all thecolor bits CR1 and CR3-CR32 are transferred to a plurality of addressedmemory cells as previously described for the unmasked submode. Inresponse to the set color bit CR2, the mask circuit 324 activates themask signal {overscore (M2)} disabling the buffer BUF2. When the bufferBUF2 is disabled, the color bit CR2 is masked from the multiplexer MUX2,which, in turn, masks the four bits of data normally transferred throughthe write drivers WD5-WD8 to the data line I/O5, I/O6, I/O7, and I/O8,respectively. Thus, the set mask bit MR2 masks the color bit CR2 fromfour addressed memory cells in the arrays 306-320. Each set mask bitMR1-MR32 similarly masks the associated color bit CR1-CR32 from fouraddressed memory cells in the arrays 306-320. Thus, during thebit-masked submode, the mask bits MR1-MR32 may be utilized to maskselected ones of the color bits CR1-CR32 from four corresponding memorycells in the arrays 306-320

The block write circuit 304 performs block write data transfers in thememory device 300 having the wide internal data path 302. During theblock write mode, each color bit CR1-CR32 is transferred to fouraddressed memory cells in the arrays 306-320 subject to the maskingsignals {overscore (M1)}-{overscore (M32)} from the mask circuit 324.The block write circuit 304 also performs bit masking of selected colorbits CR1-CR32 along with byte masking of bytes of the color bitsCR1-CR32 in the block write mode. With the block write circuit 304, thetime it takes to perform a block write data transfer is reduced. This istrue because a single digit line DL and corresponding addressed memorycell is coupled to each of the input/output lines I/O1-I/O128. Thus,each of the write drivers WD1-WD128 drives the load presented by asingle digit line DL coupled to the associated input/output lineI/O1-I/O128, just as it would during a conventional write data transfer.In contrast, as previously described with reference to FIG. 1, in priorart block write circuits a plurality of digit lines are coupled to eachof the input/output lines I/O1-I/O128, and a single write driver mustdrive the larger load presented by these multiple digit lines,increasing thetime it takes to perform a block write data transfer.

It should be noted that during block write transfers, the address decodecircuitry could activate multiple column select signals CSEL-CSELN foreach of the arrays 306-320 and thereby couple multiple digit lines toeach of the input/output lines I/O1-I/O128. Coupling multiple digitlines to each of the input/output lines I/O1-I/O128 would increase thenumber of memory cells to which data is transferred during the blockwrite mode. For example, in the array 318 the column select signalsCSEL1 and CSELX may be simultaneously activated, coupling the digitlines DL1-DL32 and DLN-32-DLN to the respective input/output linesI/O97-I/O128. Alteratively, the column select signals CSEL1 for thearrays 318,320 may be simultaneously activated, coupling the digit linesDL1-DL32 in each of the arrays 318,320 to the respective input/outputlines I/O97-I/O128. In this embodiment, however, one skilled in the artwill realize the time for performing block write transfers may increase,and column masking, which will be discussed below, will also not bepossible among multiple memory cells coupled through digit lines to acommon input/output line.

In an alternative embodiment of the block write circuit 304, column masksignals CMASK are applied to each of the multiplexers MUX1-MUX32,enabling the block write circuit 304 to perform the equivalent of columnmasking during block write operations, as will now be explained in moredetail. Once again, the signal CMASK is shown applied only to themultiplexer MUX32 merely to simplify FIG. 2. In response to the columnmask signals CMASK, each of the multiplexers MUX1-MUX32 operates duringthe block write mode to isolate selected ones of its outputs from itsinput, thereby enabling the equivalent of column masking to be performedduring the block write mode. For example, assume the block write circuit304 operates in the block write mode and the mask signal {overscore(M32)} is inactive high enabling the buffer BUF32, which applies thecolor bit CR32 to the input of the multiplexer MUX32. In thisembodiment, during the block write mode the multiplexer MUX32selectively masks the color bit CR32 from the respective input/outputlines I/O125, I/O126, I/O127, and I/O128 in response to the mask signalsCMASK. In this way, the multiplexer MUX32 performs the equivalent ofcolumn masking since the color bit CR32 may be masked from individualaddressed memory cells during the block write mode.

The block write circuit 304 of FIG. 2 may be utilized in any memorydevice having a wide internal data path, such as an Embedded DRAM or apacketized DRAM like an SLDRAM. FIG. 3 illustrates one application ofthe block write circuit 304 in an Embedded DRAM 400. The Embedded DRAM400 is an integrated circuit in which logic circuitry 402 and an SGRAM404 including the block write circuit 304 are formed in a semiconductorsubstrate 405. In other words, the logic circuitry 402 is “embedded” inthe same semiconductor substrate 405 in which the SGRAM 404 is formed.The fabrication of the Embedded DRAM 400 has become possible due toadvances in the design and fabrication of integrated circuits that havesignificantly reduced the sizes of transistors and other componentsforming such integrated circuits. Such size reductions have accordinglyincreased the density of transistors and other components that may beformed in a semiconductor substrate of a given size.

In the Embedded DRAM 400, the logic circuitry 402 may be designed toperform a specific function, or may be more general purpose circuitry,such as a microprocessor performing a variety of different tasks. Thelogic circuitry 402 is coupled to external terminals 411 to communicatewith external circuitry (not shown in FIG. 3) coupled to the EmbeddedDRAM 400, and also develops address, data, and control signals totransfer data to and from the SGRAM 404. The SGRAM 404 includes twomemory banks, BANK0 and BANK1, each bank including the arrays 306-320and coupled to the block write circuit 304 through the wide data path302. The SGRAM 404 further includes the mask register 326 and colorregister 322 that store and apply the mask bits MR1-MR32 and color bitsCR1-CR32, respectively, to the block write circuit 304. An addressdecoder 406 receives address signals on an address bus 408 and outputsdecoded address signals to the arrays 306-320 and block write circuit304, and a read/write circuit 410 transfers data between a data bus 412and the block write circuit 304. In addition, the read/write circuit 410also transfers mask and color data placed on the data bus 412 to themask register 326 and color register 322, respectively.

A control circuit 414 receives control signals applied on a control bus416 and controls the arrays 306-320, block write circuit 304, read/writecircuit 410, and other components in the SGRAM 404 in response to thesecontrol signals. The control circuit 414 also receives the byte masksignals DQM0-3, a special function signal DSF, and an external clocksignal CLK that drives the control circuit 414 during data transferoperations. In the SGRAM 404, all operations are referenced to aparticular edge of the external clock signal CLK, typically the risingedge, as known in the art.

The control circuit 414 receives a number of command signals on thecontrol bus 416 that define the operation to be executed by the SGRAM404. These command signals typically include a chip selecting signal{overscore (CS)}, write enable signal {overscore (WE)}, column addressstrobe signal {overscore (CAS)}, and row address strobe signal{overscore (RAS)}. Specific combinations of these signals defineparticular data transfer commands of the SGRAM 404 such as ACTIVE,PRECHARGE, READ, and WRITE as known in the art. In addition, certainones of these commands in combination with the special function signalDSF and byte mask signals DQM0-3 places the SGRAM 404 in the block writemode and mask data applied on the data bus 412, as will be explained inmore detail below. Typically, during standard ACTIVE and WRITE commands,the special function signal DSF is maintained inactive low. When anactive special function signal DSF is applied coincident with an ACTIVEcommand, the SGRAM 404 applies the mask stored in the mask register 326to data applied on the data bus 412 during a subsequent WRITE command.Similarly, when the special function signal DSF is active coincidentwith an applied WRITE command, the SGRAM 404 operates in the block writemode to transfer color bits stored in the color register 322 toaddressed memory cells in the arrays 306-320. In response to the bytemask signals DQM0-3, the control circuit 414 controls the read/writecircuit 410 to mask bytes of data as previously described.

In operation, the logic circuitry 402 applies address, data, and controlsignals on the respective busses 408, 412, and 416, and drives theexternal clock signal CLK to transfer data to and from the SGRAM 404.During a read data transfer operation, the logic circuitry 402 appliesan ACTIVE command to the SGRAM 404 including a row address and bankaddress placed on the address bus 408. In response to the row and bankaddresses, the address decoder 406 decodes these addresses and activatesthe corresponding bank of the arrays 306-320 and the corresponding rowof memory cells within that bank. The logic circuitry 402 thereafterapplies a READ command to the SGRAM 404 including a column and bankaddresses applied on the address bus 408. The bank address portion ofthe READ command enables multiple banks in the SGRAM 404 to be opened,and data read from selected ones of those open banks. In response to thecolumn address, the address decoder 406 accesses corresponding memorycells within the activated row in the corresponding banks. The datastored in the accessed memory cells is thereafter transferred over thewide data path 302 to the read/write circuit 410, which, in turn, placesthe data on the data bus 412 where it is read by the logic circuitry 402The logic circuitry 402 may also activate selected ones of the byte masksignals DQM0-3 during a read cycle to mask corresponding bytes of datato typically placed on the data bus 412 during the read cycle. Asunderstood by one skilled in the art, during a read cycle the byte masksignals DQM0-3 are typically utilized by the logic circuitry 402 toprevent data contention on the data bus 412 when a read cycle isimmediately followed by a write cycle.

During a write cycle, the logic circuitry 402 once again applies anACTIVE command to the SGRAM 404 to activate a corresponding bank of thearrays 306-320 and a row within that bank. After applying the ACTIVEcommand, the logic circuitry 402 applies a WRITE command to the SGRAM404 including column and bank addresses on the address 408 and writedata on the data bus 412. Once again, the address decoder 406 decodesthe column address and accesses corresponding memory cells in theactivated row of the corresponding bank. The data placed on the data bus412 is then transferred through the read/write circuit 410, block writecircuit 304, and across the wide internal data path 302 to addressedmemory cells in the arrays 306-320. During a conventional write cycle,the logic circuitry 402 controls the byte mask signals DQM0-3 toselectively mask bytes of data applied on the data bus 412, aspreviously described. In addition, the logic circuitry 402 may also maskindividual bits of data applied on the data bus 412 using the mask bitsMR1-MR32 stored in the mask register 326.

As understood by one skilled in the art, the logic circuitry 402 appliesspecial load commands to the SGRAM 404 to load the mask bits MR1-MR32 inthe same mask register 326, and must load the desired mask bits beforemasking write data applied on the data bus 412. In order to mask dataplaced on the data bus 412 using the mask bits MR1-MR32 stored in themask register 326, the logic circuitry 402 must drive the specialfunction signal DSF active coincident with applying the ACTIVE command,which is typically referred to as an ACTIVE with WPB command. The blockwrite circuit 304 masks all write data placed on the data bus 412according to the mask bits MR1-MR32 after such an ACTIVE with WPBcommand is applied, and until a subsequent conventional ACTIVE commandis applied. The logic circuitry 402 controls the byte mask signalsSQM0-3 and applies ACTIVE with WPB commands to mask write data placed onthe data bus 412 as desired.

To place the SGRAM 404 in the block write mode, the logic circuitry 402first applies an ACTIVE command to activate a bank and a addressed rowwithin that bank. After applying the ACTIVE command, the logic circuitry402 applies a block write command by driving the special function signalDSF active coincident with applying a WRITE command to the SGRAM 404.Column mask data may also be applied on the data bus 412 coincident withthe block write command, causing the block write circuit 304 to performcolumn masking as previously described. In response to the activespecial function signal DSF registered coincident with the WRITEcommand, the control circuit 414 places the block write circuit 304 inthe block write mode of operation. The WRITE command portion of theblock write command again includes column and bank addresses on theaddress bus 408. The address decoder 406 decodes the column and bankaddresses and activates corresponding blocks of memory cells in thecorresponding bank. The block write circuit 304 operates as previouslydescribed to transfer the color bits CR1-CR32 stored in the colorregister 322 to the addressed blocks of memory cells in the arrays306-320. Once again, the logic circuitry 402 must apply special loadcommands to the SGRAM 404 to load the desired color bits CR1-CR32 beforeplacing the SGRAM 404 in the block write mode of operation. During theblock write mode of operation, the logic circuitry 402 may again utilizethe byte mask signals DQM0-3 and mask bits MR1-MR32 stored in the maskregister 326 to selectively mask the color bits CR1-CR32 stored in thecolor register 322, as previously described.

FIG. 4 is a block diagram of a computer system 500 including theembedded DRAM 400 of FIG. 3. The computer system 500 includes computercircuitry 502 for performing various computing functions, such asexecuting specific software to perform specific calculations or tasks.In the computer system 500, the embedded DRAM 400 typically has itslogic circuitry 402 designed to perform a specific function, such ashigh-resolution graphics or high-speed communication operations. Thecomputer system 500 further includes one or more input devices 504, suchas a keyboard or a mouse, coupled to the computer circuitry 502 to allowan operator to interface with the computer system 500. Typically, thecomputer system 500 includes one or more output devices 506 coupled tothe computer circuitry 502, such output devices typically being aprinter or a video terminal. One or more data storage devices 508 arealso typically coupled to the computer circuitry 502 to store data orretrieve data from the external storage media (not shown in FIG. 5).Examples of typical data storage devices 508 include hard and floppydisks, tape cassettes, and compact disk read-only memories (“CD-ROMs”).

It is to be understood that even though various embodiments andadvantages of the present invention have been set forth in the foregoingdescription, the above disclosure is illustrative only, and changes maybe made in detail, and yet remain within the broad principles of theinvention. Therefore, the present invention is to be limited only by theappended claims.

We claim:
 1. A block write circuit in a memory device including at leastone array of memory cells, each of the at least one array of memorycells including a plurality of memory cells arranged in rows and columnsand a plurality of digit lines, each digit line coupled to a pluralityof memory cells in an associated column, the block write circuitcomprising: a plurality of input/output lines; a switch circuit coupledbetween the input/output lines and the digit lines, the switch circuitselectively coupling at least one digit line to each input/output lineresponsive to an address signal during a block write mode of operation;a plurality of driver circuits, each driver circuit including an inputan output coupled to a respective input/output line, and developing adata signal on its output in response to a data signal applied on itsinput; and a multiplexer circuit having an input adapted to receive adata signal, and a plurality of outputs coupled to respective inputs ofthe driver circuits, the multiplexer circuit coupling its input to itsoutputs responsive to a control signal during the block write mode ofoperation.
 2. The block write circuit of claim 1 wherein the switchcircuit couples a single digit line to each input/output line during theblock write mode of operation.
 3. The block write circuit of claim 1wherein the input of the multiplexer each buffer circuit receives arespective color bit data signal from a color register during the blockwrite mode of operation.
 4. The block write circuit of claim 1 whereinthe switch circuit includes a plurality of column select transistors,each column select transistor having signal terminals coupled between arespective digit line and a corresponding input/output line having itscontrol terminal adapted to receive a column select signal.
 5. The blockwrite circuit of claim 1 wherein the multiplexer circuit includes oneinput and four outputs.
 6. A block write circuit in a memory deviceincluding at least one array of memory cells, each of the at least onearray of memory cells including a plurality of memory cells arranged inrows and columns and a plurality of digit lines, each digit line coupledto a plurality of memory cells in an associated column, the block writecircuit comprising: a plurality of input/output lines; a switch circuitcoupled between the input/output lines and the digit lines, the switchcircuit selectively coupling at least one digit line to eachinput/output line responsive to an address signal during a block writemode of operation; a plurality of driver circuits, each driver circuitincluding an input, and an output coupled to a respective input/outputlines, and developing a data signal on its output in response to a datasignal applied on its input; and a multiplexer circuit having an inputadapted to receive a data signal, and a plurality of outputs coupled torespective inputs of the driver circuits, the multiplexer circuitcoupling its input to selected ones of its outputs and isolating itsinput from the other ones of its outputs responsive to first signalsduring the block write mode of operation.
 7. The block write circuit ofclaim 6 1wherein the first signals includecontrol signal includes ablock write signal and a plurality of column mask signals.
 8. The blockwrite circuit of claim 6 wherein the switch circuit couples a singledigit line to each input/output line during the block write mode ofoperation.
 9. The block write circuit of claim 6 wherein the input ofthe multiplexer circuit receives a color bit data signal from a colorregister during the block write mode of operation.
 10. The block writecircuit of claim 6 wherein the switch circuit includes a plurality ofcolumn select transistors, each column select transistor having signalterminals coupled between a respective digit line and a correspondinginput/output line, and having a control terminal adapted to receive acolumn select signal.
 11. The block write circuit of claim 6 wherein themultiplexer circuit includes one input and four outputs.
 12. A blockwrite circuit in a memory device, comprising: a plurality of dataterminals adapted to receive respective data signals; a plurality ofarrays groups, each array group including a plurality of arrays and eacharray including a plurality of memory cells arranged in rows and columnsand a plurality of digit lines, each digit line coupled to a pluralityof memory cells in an associated column; a plurality of input/outputline groups, each input/output line group including a plurality ofinput/output lines; a plurality of switch circuits, each switch circuitcoupled between the input/output lines of a respective input/output linegroup and the digit lines of the arrays in an associated array group,and each switch circuit selectively coupling at least one digit line toeach input/output line responsive to address signals during a blockwrite mode of operation; a plurality of write driver groups, each writedriver group including a plurality of write driver circuits havingoutputs coupled to respective input/output lines in an associatedinput/output line group, each write driver circuit including an input,and developing a data signal on its output responsive to a data signalapplied on its input; and a multiplexer circuit including a plurality ofinputs coupled to respective data terminals, and a plurality of outputsubgroups, each output subgroup associated with a respective input, andeach output group including a plurality of outputs coupled to respectiveinputs of the write driver circuits in an associated write driver group,the multiplexer circuit operable responsive to the control signal in ablock write mode to couple each of its inputs to the outputs in theassociated output subgroup.
 13. The block write circuit of claim 12wherein each switch circuit couples a single digit line to eachinput/output line during the block write mode of operation.
 14. Theblock write circuit of claim 12 wherein during the block write mode ofoperation each of the inputs of the multiplexer buffer circuit receivesa respective color bit data signal from a corresponding storage locationin a color register.
 15. The block write circuit of claim 12 whereineach switch circuit includes a plurality of column select transistors,each column select transistor having signal terminals coupled between arespective digit line and a corresponding input/output line, and havinga control terminal adapted to receive a column select signal.
 16. Theblock write circuit of claim 12 wherein the multiplexer circuit furtheroperates in the block write mode responsive to column masking signals toisolate each input from selected ones of the outputs in the associatedoutput subgroup.
 17. The block write circuit of claim 12 wherein theplurality of array and input/output line groups include four array andfour input/output line groups, respectively, each input/output linegroup including thirty-two input/output lines, the plurality of dataterminals including thirty-two data terminals, each write driver groupincluding thirty-two write drivers, and each output subgroup of themultiplexer circuit including four outputs.
 18. The block write circuitof claim 12 wherein the multiplexer circuit includes one multiplexer foreach output subgroup.
 19. The block write circuit of claim 18 whereineach multiplexer includes one input and four outputs.
 20. A block writecircuit in a memory device including a plurality of data terminals andan array including a plurality of memory cells arranged in rows andcolumns and having a plurality of digit lines, each digit line coupledto a plurality of memory cells in an associated column, the block writecircuit comprising: a plurality of input/output lines; a switch circuitcoupled between the input/output lines and the digit lines, the switchcircuit selectively coupling at least one digit line to eachinput/output line responsive to an address signal during a block writemode of operation; a plurality of write driver circuits, each writedriver circuit having an input, an output coupled to a respectiveinput/output line, and developing a data signal on its output inresponse to a data signal applied on its input; a plurality of buffercircuits, each buffer circuit including an output, an input coupled to arespective data terminal, and an enable terminal adapted to receive anenable signal, each buffer circuit developing a signal on its output inresponse to a signal applied on its input when the enable signal isactive, and placing its output in a high impedance state when the enablesignal is inactive; a masking circuit adapted to receive a plurality ofmasking signals, and applying a plurality of enable signals torespective enable terminals of the buffer circuits in response to themasking signals; and a multiplexer circuit having a plurality of inputscoupled to respective outputs of the buffer circuits, and a plurality ofoutputs coupled to respective inputs of the write driver circuits, themultiplexer circuit operable responsive to a control signal in the blockwrite mode to couple each of its inputs to a plurality of associatedoutputs.
 21. The block write circuit of claim 20 wherein the multiplexercircuit further operates during the block write mode to isolate eachinput from selected ones of the associated outputs responsive to columnmask signals.
 22. The block write circuit of claim 20 wherein themultiplexer circuit operates during the block write mode to couple eachof its inputs to four associated outputs.
 23. The block write circuit ofclaim 20 wherein the masking circuit is adapted to receive a pluralityof byte-mask signals and bit-mask signals, and operates to enable ordisable eight corresponding enable signals in response to each byte-masksignal, and enables or disables respective enable signals in response tocorresponding bit-mask signals.
 24. The block write circuit of claim 20wherein the masking circuit comprises a plurality of AND gates, each ANDgate including a first input adapted to receive a respective bit-masksignal and a second input adapted to receive a respective byte-masksignal, and developing a corresponding enable signal on its output. 25.The block write circuit of claim 20 wherein the input of each buffercircuit is adapted to receive a respective one of a plurality of colorbit signals stored in a color register.
 26. The block write circuit ofclaim 20 wherein the switch circuit couples one digit line to eachinput/output line during the block write mode of operation.
 27. A memorydevice, comprising: an address bus adapted to receive address signals; acontrol bus adapted to receive control signals; a data bus adapted toreceive at least one data signal; at least one array of memory cellsincluding a plurality of memory cells arranged in rows and columns and aplurality of digit lines, each digit line coupled to the memory cells inassociated column; an address decoder coupled to the address bus and theat least one array; a control circuit coupled to the control bus; aread/write circuit coupled to the data bus; and a block write circuitcoupled to the address decoder and control circuit, the block writecircuit comprising: a plurality of input/output lines; a switch circuitcoupled between the input/output lines and the digit lines of the atleast one array, the switch circuit selectively coupling at least onedigit line to each input/output line responsive to an address signalduring a block write mode of operation; a plurality of driver circuits,each driver circuit including an input, and an output coupled to arespective input/output line, and developing a data signal on its outputin response to a data signal applied on its input; and a multiplexercircuit having an input adapted to receive a data signal, and aplurality of outputs coupled to respective inputs of the drivercircuits, the multiplexer circuit coupling its input to its outputsresponsive to a control signal during the block write mode of operation.28. The memory device of claim 27 wherein the memory device includes aDRAM.
 29. The memory device of claim 27 wherein the multiplexer circuitfurther operates in a column mask mode to isolate selected ones of itsoutput from its input.
 30. The memory device of claim 27 wherein themultiplexer each buffer circuit receives on its input a color bit datasignal stored in a color register.
 31. The memory device of claim 27wherein the switch circuit couples a single digit line to eachinput/output line.
 32. A memory device, comprising: an address busadapted to receive address signals; a control bus adapted to receivecontrol signals; a data bus adapted to receive at least one data signal;at least one array of memory cells including a plurality of memory cellsarranged in rows and columns and a plurality of digit lines, each digitline coupled to the memory cells in associated column; an addressdecoder coupled to the address bus and the at least one array; a controlcircuit coupled to the control bus; a read/write circuit coupled to thedata bus; and a block write circuit coupled to the address decoder andcontrol circuit, the block write circuit comprising: a plurality ofinput/output lines; a switch circuit coupled between the input/outputlines and the digit lines of the at least one array, the switch circuitselectively coupling at least one digit line to each input/output lineresponsive to an address signal during a block write mode of operation;a plurality of driver circuits, each driver circuit including an input,and an output coupled to a respective input/output line, and developinga data signal on its output in response to a data signal applied on itsinput; a plurality of buffer circuits, each buffer circuit including anoutput, an input coupled to a respective data terminal of the data bus,and an enable terminal adapted to receive an enable signal, each buffercircuit developing a signal on its output in response to a signalapplied on its input when the enable signal is active, and placing itsoutput in a high impedance state when the enable signal is inactive; amasking circuit coupled to the data bus and adapted to receive aplurality of masking signals and applying a plurality of enable signalsto respective enable terminals of the buffer circuits in response to themasking signals; a multiplexer circuit having a plurality of inputscoupled to respective outputs of the buffer circuits, and a plurality ofoutputs coupled to respective inputs of the write driver circuits, themultiplexer circuit operable responsive to a control signal to coupleeach of its inputs to a plurality of associated outputs in the blockwrite mode; and a color register coupled to the data bus and to theinputs of the multiplexer circuit, the color register operable to storecolor data bits applied on the data bus and apply color data bits to theinputs of the multiplexer circuit during the block write mode.
 33. Thememory device of claim 32 wherein the memory device includes a DRAM. 34.The memory device of claim 32 wherein the multiplexer circuit furtheroperates in a column mask mode to isolate each of its inputs fromselected ones of the associated outputs responsive to column masksignals.
 35. The memory device of claim 32 wherein the switch circuitcouples a single digit line to each input/output line during the blockwrite mode.
 36. An embedded memory device, comprising: a logic circuitdeveloping address, and control signals on respective internal address,data and control busses, and operable to perform a desired function; anda memory device coupled to the logic circuit through the internaladdress, control, and data busses, the memory device comprising: anaddress bus adapted to receive address signals; a control bus adapted toreceive control signals; a data bus adapted to receive at least one datasignal; at least one array of memory cells including a plurality ofmemory cells arranged in rows and columns and a plurality of digitlines, each digit line coupled to the memory cells in an associatedcolumn; an address decoder coupled to the address bus and the at leastone array; a control circuit coupled to the control bus; a read/writecircuit coupled to the data bus; and a block write circuit coupled tothe address decoder and control circuit, the block write circuitcomprising: a plurality of input/output lines; a switch circuit coupledbetween the input/output lines and the digit lines of the at least onearray, the switch circuit selectively coupling at least one digit lineto each input/output line responsive to an address signal during a blockwrite mode of operation; a plurality of driver circuits, each drivercircuit including an input, and an output coupled to a respectiveinput/output line, and developing a data signal on its output inresponse to a data signal applied on its input; and a multiplexercircuit having an input adapted to receive a data signal, and aplurality of outputs coupled to respective inputs of the drivercircuits, the multiplexer circuit coupling its input to its outputsresponsive to a control signal during the block write mode of operation.37. The embedded memory device of claim 36 wherein the memory deviceincludes a DRAM.
 38. The embedded memory device of claim 36 wherein themultiplexer circuit further operates in a column mask mode to isolateselected ones of its outputs from its input.
 39. The embedded memorydevice of claim 36 wherein the multiplexer each buffer circuit receiveson its input a color bit data signal stored in a color register.
 40. Theembedded memory device of claim 36 wherein the switch circuit couples asingle digit line to each input/output line.
 41. A computer system,comprising: a data input device; a data output device; and computingcircuitry coupled to the data input and output devices, the computingcircuitry including an embedded memory device, comprising: a logiccircuit operable to perform a desired function, and operable to developaddress, data, and control signals on respective internal address, dataand control busses; and a memory device coupled to the logic circuitthrough the internal address, control, and data busses, the memorydevice comprising: an address bus adapted to receive address signals; acontrol bus adapted to receive control signals; a data bus adapted toreceive at least one data signal; at least one array of memory cellsincluding a plurality of memory cells arranged in rows and columns and aplurality of digit lines, each digit line coupled to the memory cells inan associated column; an address decoder coupled to the address bus andthe at least one array; a control circuit coupled to the control bus; aread/write circuit coupled to the data bus; and a block write circuitcoupled to the address decoder and control circuit, the block writecircuit comprising: a plurality of input/output lines; a switch circuitcoupled between the input/output lines and the digit lines of the atleast one array, the switch circuit selectively coupling at least onedigit line to each input/output line responsive to an address signalduring a block write mode of operation; a plurality of driver circuits,each driver circuit including an input, and an output coupled to arespective input/output line, and developing a data signal on its outputin response to a data signal applied on its input; and a multiplexercircuit having an input adapted to receive a data signal, and aplurality of outputs coupled to respective inputs of the drivercircuits, the multiplexer circuit coupling its input to its outputsresponsive to a control signal during the block write mode of operation.42. The computer system of claim 41 wherein the memory device includes aDRAM.
 43. A method for writing a block of data to a plurality of memorycells in a memory device including a data terminal and having an arrayof memry cells, the array including a plurality of memory cells arrangedin rows and columns and a plurality of digit lines, each digit linecoupled to the digit lines in an associated column, and a plurality ofinput/output lines being coupled through a switch circuit to the digitlines, comprising: activating a row of memory cells in the array;coupling the digit lines associated with an addressed block of memorycells to respective input/output lines, each digit line being coupled toa different input/output line; and transferring a data signal applied onthe data terminal over the respective input/output lines and over thecorresponding digit lines to each of the memory cells in the addressedblock.
 44. The memory of claim 43 wherein the addressed block of memorycells includes thirty-two memory cells, and each of the thirty-two digitlines associated with the memory cells in the addressed block is coupledto a respective one of thirty-two input/output lines.
 45. The method ofclaim 43 wherein a color bit data signal is transferred to the memorycells in the addressed block.
 46. A method for writing a block of datato a plurality of memory cells in a memory device including a dataterminal and having an array of memory cells, the array including aplurality of memory cells arranged in rows and columns and a pluralityof digit lines, each digit line coupled to the digit lines in anassociated column, and a plurality of input/output lines being coupledthrough a switch circuit to the digit lines, comprising: activating arow of memory cells in the array; coupling the digit lines associatedwith an addressed block of memory cells to respective input/outputlines, each digit line being coupled to a different input/output line;and transferring a data signal applied on the data terminal over therespective input/output lines and over the corresponding digit lines toeach of the memory cells in the addressed block; and isolating the datasignal from selected input/output lines to thereby mask the data signalfrom corresponding memory cells in the addressed block.
 47. The methodof claim 46 wherein the addressed block of memory cells includesthirty-two memory cells, and each of the thirty-two digit linesassociated with the memory cells in the addressed block is coupled to arespective one of thirty-two input/output lines.
 48. The method of claim46 wherein the data signal is a color bit data signal.
 49. The method ofclaim 46 wherein the data signal is masked from bytes of memory cellswithin the addressed block responsive to byte-mask signals.
 50. A methodfor writing a block of data to a plurality of memory cells in a memorydevice including a data terminal and having an array of memory cells,the array including a plurality of memory cells arranged in rows andcolumns and a plurality of digit lines, each digit line coupled to thedigit lines in an associated column, and a plurality of input/outputlines being coupled through a switch circuit to the digit lines,comprising: activating a plurality of memory cells in the array; placingthe memory device in a block write mode; coupling at least some of theactivated memory cells through the associated digit lines to respectiveinput/output lines; and transferring a data signal applied on the dataterminal over respective input/output lines to memory cells coupled tothe input/output lines.
 51. The method of claim 50 wherein the datasignal includes a color bit data signal applied to the data terminal.52. A block write circuit in a memory device including at least onearray of memory cells, each of the at least one array of memory cellsincluding a plurality of memory cells arranged in rows and columns and aplurality of digit lines, each digit line coupled to a plurality ofmemory cells in an associated column, the block write circuitcomprising: a plurality of input/output lines; a switch circuit coupledbetween the input/output lines and the digit lines, the switch circuitselectively coupling at least one digit line to each input/output lineresponsive to an address signal during a block write mode of operation;a plurality of driver circuits, each driver circuit including an input,an output coupled to a respective input/output line, and developing adata signal on its output in response to a data signal applied on itsinput; a plurality of buffer circuits, each buffer circuit including anoutput, an input coupled to a respective data terminal, and an enableterminal adapted to receive an enable signal, each buffer circuitdeveloping a signal on its output in response to a signal applied on itsinput when the enable signal is active, and placing its output in a highimpedance state when the enable signal is inactive; a masking circuitadapted to receive a plurality of masking signals, and applying aplurality of enable signals to respective enable terminals of the buffercircuits in response to the masking signals; and a multiplexer circuithaving an input adapted to receive a data signal, a control terminaladapted to receive a control signal, and a plurality of outputs coupledto respective inputs of the driver circuits, the multiplexer circuitcoupling the input to selected outputs responsive to the control signalduring the block write mode of operation.
 53. The block write circuit ofclaim 52 wherein the switch circuit couples a single digit line to eachinput/output line during the block write mode of operation.
 54. Theblock write circuit of claim 52 wherein the input of each buffer circuitreceives a respective color bit data signal from a color register duringthe block write mode of operation.
 55. The block write circuit of claim52 wherein the switch circuit includes a plurality of column selecttransistors, each column select transistor having signal terminalscoupled between a respective digit line and a corresponding input/outputline having its control terminal adapted to receive a column selectsignal.
 56. The block write circuit of claim 52 wherein the multiplexercircuit includes one input and four outputs.
 57. A block write circuitin a memory device, comprising: a plurality of data terminals adapted toreceive respective data signals; a plurality of array groups, each arraygroup including a plurality of arrays and each array including aplurality of memory cells arranged in rows and columns and a pluralityof digit lines, each digit line coupled to a plurality of memory cellsin an associated column; a plurality of input/output line groups, eachinput/output line group including a plurality of input/output lines; aplurality of switch circuits, each switch circuit coupled between theinput/output lines of a respective input/output line group and the digitlines of the arrays in an associated array group, and each switchcircuit selectively coupling at least one digit line to eachinput/output line responsive to address signals during a block writemode of operation; a plurality of write driver groups, each write drivergroup including a plurality of write driver circuits having outputscoupled to respective input/output lines in an associated input/outputline group, each write driver circuit including an input, and developinga data signal on its output responsive to a data signal applied on itsinput; a plurality of buffer circuits, each buffer circuit including anoutput, an input coupled to a respective data terminal, and an enableterminal adapted to receive an enable signal, each buffer circuitdeveloping a signal on its output in response to a signal applied on itsinput when the enable signal is active, and placing its output in a highimpedance state when the enable signal is inactive; a masking circuitadapted to receive a plurality of masking signals, and applying aplurality of enable signals to respective enable terminals of the buffercircuits in response to the masking signals; and a multiplexer circuitincluding a plurality of inputs coupled to respective outputs of thebuffer circuits and including a plurality of output subgroups, eachoutput subgroup, associated with a respective input, and each outputgroup including a plurality of outputs coupled to respective inputs ofthe write driver circuits in an associated write driver group, themultiplexer circuit operable responsive to the control signal in a blockwrite mode to couple each of its input to the outputs in the associatedoutput subgroup.
 58. The block write circuit of claim 57 wherein eachswitch circuit couples a single digit line to each input/output lineduring the block write mode of operation.
 59. The block write circuit ofclaim 57 wherein during the block write mode of operation each buffercircuit receives a respective color bit data signal from a correspondingstorage location in a color register.
 60. The block write circuit ofclaim 57 wherein each switch circuit includes a plurality of columnselect transistors, each column select transistor having signalterminals coupled between a respective digit line and a correspondinginput/output line, and having a control terminal adapted to receive acolumn select signal.
 61. The block write circuit of claim 57 whereinthe multiplexer circuit further operates in the block write moderesponsive to column mask signals to isolate each input from selectedones of the outputs in the associated output subgroup.
 62. The blockwrite circuit of claim 57 wherein the plurality of array andinput/output line groups include four array and four input/output linegroups, respectively, each input/output line group including thirty-twoinput/output lines, the plurality of data terminals including thirty-twodata terminals, each write driver group including thirty-two writedrivers, and each output subgroup of the multiplexer circuit includingfour outputs.
 63. The block write circuit of claim 57 wherein themultiplexer circuit includes one multiplexer for each output subgroup.64. The block write circuit of claim 63 wherein each multiplexerincludes one input and four outputs.
 65. A memory device, comprising: anaddress bus adapted to receive address signals; a control bus adapted toreceive control signals; a data bus adapted to receive at least one datasignal; at least one array of memory cells including a plurality ofmemory cells arranged in rows and columns and a plurality of digitlines, each digit line coupled to the memory cells in an associatedcolumn; an address decoder coupled to the address bus and the at leastone array; a control circuit coupled to the control bus; a read/writecircuit coupled to the data bus; and a block write circuit coupled tothe address decoder and control circuit, the block write comprising: aplurality of input/output lines; a switch circuit coupled between theinput/output lines and the digit lines of the at least one array, theswitch circuit selectively coupling at least one digit line to eachinput/output line responsive to an address signal during a block writemode of operation; a plurality of driver circuits, each driver circuitincluding an input, and an output coupled to a respective input/outputline, and developing a data signal on its output in response to a datasignal applied on its input; a plurality of buffer circuits, each buffercircuit including an output, an input coupled to a respective dataterminal, and an enable terminal adapted to receive an enable signal,each buffer circuit developing a signal on its output in response to asignal applied on its input when the enable signal is active, andplacing its output in a high impedance state when the enable signal isinactive; a masking circuit adapted to receive a plurality of maskingsignals, and applying a plurality of enable signals to respective enableterminals of the buffer circuits in response to the masking signals; anda multiplexer circuit having an input adapted to receive a data signal,a control terminal adapted to receive a control signal, and a pluralityof outputs connected to respective inputs of the driver circuits, themultiplexer circuit coupling the input to selected outputs respective tothe control signal during the block write mode of operation.
 66. Thememory device of claim 65 wherein the memory device includes a DRAM. 67.The memory device of claim 65 wherein the multiplexer circuit furtheroperates in a column mask mode to isolate selected ones of its outputsfrom its input.
 68. The memory device of claim 65 wherein each buffercircuit receives on its input a color bit data signal stored in a colorregister.
 69. The memory device of claim 65 wherein the switch circuitcouples a single digit line to each input/output line.
 70. A method forwriting a block of data to a plurality of memory cells in a memorydevice including a data terminal and having an array of memory cells,the array including a plurality of memory cells arranged in rows andcolumns and a plurality of digit lines, each digit line being coupled tothe memory cells in an associated column, and the memory deviceincluding a plurality of input/output lines, the method comprising:activating a row of memory cells in the array; coupling the digit linesassociated with an addressed block of memory cells to respectiveinput/output lines, each digit line being coupled to a differentinput/output line; storing a masking bit in the memory device;transferring a data signal applied on the data terminal over therespective input/output lines and over the corresponding digit lines toeach of the memory cells in the addressed block when the stored maskingbit has a first value; and masking the data signal from the memory cellsin the addressed block when the stored masking bit has a second value.71. The method of claim 70 wherein the addressed block of memory cellsincludes thirty-two memory cells, and each of the thirty-two digit linesassociated with the memory cells in the addressed block is coupled to arespective one of thirty-two input/output lines.
 72. The method of claim70 wherein a color bit data signal is transferred to the memory cells inthe addressed block.
 73. A block write circuit in a memory deviceincluding at least one array of memory cells, each of the at least onearray of memory cells including a plurality of memory cells arranged inrows and columns and a plurality of digit lines, each digit line coupledto a plurality of memory cells in an associated column, the block writecircuit comprising: a plurality of input/output lines; a switching meanscoupled between the input/output lines and the digit lines forselectively coupling at least one digit line to each input/output lineresponsive to an address signal during a block write mode of operation;a plurality of driver means each being coupled to respectiveinput/output lines for developing a data signal on an output in responseto a data signal applied on an input; a plurality of buffering meanseach being coupled to a respective data terminal for developing a signalon an output in response to a signal applied on an input when an appliedenable signal is active, and for placing the output in a high impedancestate when the enable signal is inactive; a masking means for applying aplurality of enable signals to respective enable terminals of the buffercircuits in response to a plurality of masking signals; and amultiplexing means having a plurality of outputs coupled to respectiveinputs of the driver means for coupling an input to a selected outputresponsive to a control signal during the block write mode of operation.74. The block write circuit of claim 73 wherein the switching meanscouples a single digit line to each input/output line during the blockwrite mode of operation.
 75. The block write circuit of claim 73 whereinthe input of each buffering means receives a respective color bit datasignal from a color register during the block write mode of operation.76. The block write circuit of claim 73 wherein the switching meansincludes a plurality of column selection means for coupling respectivedigit lines to the input/output lines responsive to respective columnselect signals.